There's a lot here! The following explains how to think of each line in terms of the hardware we are describing.
class Passthrough extends Module {
We declare a new module called Passthrough
. Module
is a built-in Chisel class that all hardware modules must extend. Only then will your modules get mapped to actual hardware modules in Verilog.
We declare all our input and output ports in a special val
named io
. It must be called io
and be an IO
object or instance, which requires something of the form IO(_instantiated_struct_)
, where Bundle acts like a struct.
new Bundle {
val in = Input(...)
val out = Output(...)
}
We declare a new hardware struct type (Bundle) that contains some named signals in
and out
with directions Input and Output, respectively.
We declare a signal's hardware type. In this case, both in
and out
are unsigned integers of width 4.
We connect our input port to our output port, such that io.in
drives io.out
. Note that the :=
operator is a *Chisel* operator that indicates that the right-hand signal drives the left-hand signal. It is a directioned operator.
The neat thing about hardware construction languages (HCLs) is that we can use the underlying programming language as a scripting language. For example, after declaring our Chisel module, we then use Scala to call the Chisel compiler to translate Chisel Passthrough
into Verilog Passthrough
. This process is called *elaboration*.